This invention relates to semiconductor memories, particularly those memories which utilize capacitive means for the storage of binary data.
In the description of the present invention, the term "transistor" refers to either a bipolar transistor or to a field effect transistor. When referring to the terminals of a transistor, the term "control terminal" designates the gate of a field effect transistor, and the base of a bipolar transistor; the term "input terminal" designates the source of a field effect transistor and the emitter of a bipolar transistor, and the term "output terminal" designates the drain of a field effect transistor and the collector of a bipolar transistor. Also the "state of the transistor" refers to the alternative on or off states of the transistor -- when the transistor is on, the resistance between the input and output terminals is relatively small, and conversely, when the transistor is off, the resistance between the said terminals is relatively large. The state of the transistor is controlled by the potential of the control terminal relative to the input terminal when the transistor is operated in the forward mode, and by the potential of the control terminal relative to the output terminal when the transistor is operated in the reverse mode.
The economics relevant to semiconductor random access memories make it desirable to minimize the semiconduct surface area required per bit. The semiconductor surface area required per bit includes the area of the memory cell itself, and a proportionate share of the area required for the support circuitry, access pads, and other elements required for the operation or manufacture of the memory. In the prior art, the most dense memories use dynamic types of memory cells in which a storage capacitor which may be charged to either of two different states is utilized to store binary data, and a transistor is used to provide addressable access to the storage capacitor. Since the capacitance of the storage capacitor depends directly on the surface area of the storage capacitor, the minimum size of this type of memory cell depends in part, on the size of the storage capacitor.
In the aforementioned memory cells, for a particular memory array size, the loading of the storage capacitor usually determines the minimum capacitance required. In particular, when recalling the datum stored in a memory cell, part of the charge on the storage capacitor is discharged on to a row line which interconnects a plurality of memory cells to the input of a sense amplifier. Therefore the storage capacitance must be sufficiently large so that when it is charged and then discharged on to the row line, it is capable of charging up the capacitance consisting of the parallel combination of the capacitance of the row line itself, the input capacitance of the other memory cells connected to the same row line, and the input capacitance of the sense amplifier. The voltage to which the said parallel combination of capacitors must be charged depends on the minimum voltage level sufficient to be reliably detected by the sense amplifier.
In the prior art, at least three techniques have been devised to permit reduction of the storage capacitance. The first technique is based on the observation that the number of memory cells connected to each of the row lines determines, in part, the capacitive loading of the storage capacitor. For an array with a fixed number of memory cells, simply by decreasing the number of memory cells connected to each row line, and increasing the number of row lines in the array, the capacitive loading of the storage capacitor could be decreased to a relatively small value. But considerations such as minimizing the complexity of and minimizing the semiconductor surface area required for the support circuitry, limit the number of row lines that may be used in the array, and therefore determines the number of memory cells that must be connected to each row line. However, it is possible to split the memory cells appearing in one row in to two contiguous groups, and locate the sense amplifier for each row in the break between the two groups of memory cells. By using an appropriate sense amplifier, this can be accomplished without significantly complicating the support circuitry. However the prior art does not permit this technique to be used to further subdivide the memory cells appearing in one row without greatly complicating the support circuitry.
The second technique has been to improve the sensitivity of the sense amplifiers through improved design, improved manufacture, and improved operating techniques.
A third technique which has not been adopted by most memory manufacturers is described in U.S. Pat. No. 3,764,906, dated Oct. 9, 1973 and granted to Lawrence G. Heller. In the technique described in this patent, the electrical charge lost from the storage capacitor as it charges up the loading capacitor is replaced from a fixed quantity of charge. The change in this fixed quantity of charge is then used to drive the sence amplifier.